The present invention relates generally to system-on-a-chip (SOC) applications and more particularly to on-chip buses used in such SOC applications.
Recent advances in silicon densities allow for the integration of numerous functions onto a single silicon chip. With this increased density, peripheral devices formerly attached to a processor at the card level are integrated onto the same die as the processor. As a result, chip designers must address issues traditionally handled by system designers. This type of implementation of a complex circuit on a single die is referred to as a system-on-a-chip (SOC).
Typically, an SOC contains numerous functional blocks representing a large number of logic gates. Design of such a system is realised through a macro-based approach. Macro-based design facilitates logic entry and verification, as well as re-use of macros with particular functionality. A macro is a re-usable tested design available in a library in the form of a netlist. In applications ranging from generic serial ports to complex memory controllers and processor cores, each SOC uses a number of common macros. A core is a re-usable tested design in any hardware description language like VHDL or Verilog.
Many single-chip solutions used in such applications are designed as custom chips, each with its own internal architecture. Logical units within such a chip are often difficult to extract and re-use in different applications. As a result, the same function is re-designed many times from one application to another.
Thus, a need clearly exists for an improved architecture for devices interfacing to an on-chip bus used in such SOC implementations that is able to optimise bus usage in respect of read and write data transfers.
In accordance with a first aspect of the invention, there is provided a method of optimising a bus in a Processor Local Bus (PLB) system. The method includes the steps of:
providing a master engine for performing a transfer transaction of N bytes of data on the bus of the PLB system;
determining a type of transfer to be performed by the master engine to optimize operation of the bus of the PLB system in response to a transfer request received asynchronously from a device coupled to the bus; and
transferring data asynchronously using a FIFO between the device and the bus of the PLB system dependent upon the determined type of transfer.
Preferably, the transfer request is for a read or write data transfer.
Preferably, the determining step utilizes a request type determination function:
Opt_req(t) f(c1c2, S_FIFO, arb, thr_fifo)+g(wait_AAck, wait_DAck)+h(t, latmr, xfer_cnt, cnt_fifo, pend_req, pend_pri),
where f( ) is a function of:
c1c2=a clock frequency ratio between PLB clock c1 and device clock c2,
S_FIFO=size of FIFO used for asynchronous interface,
arb=PLB arbitration type, single or two cycle,
thr_fifo=threshold of FIFO;
g( ) is a function of slave address acknowledgment wait state wait_AAck and slave data acknowledgment wait state wait_Dack;
h( ) is a function of:
t=time,
latmr=PLB master""s latency timer count value at time t,
xfer_cnt=number of data transfers remaining at time t, to complete the device requested number of transfers,
cnt_fifo=occupancy of FIFO at time t,
pend_req=pending request at time t, and
pend_pri=pending request priority at time t.
Preferably, the method further includes the step of generating a transfer request. The generating step may include the steps of: checking a transfer count indicating the number of transfers remaining; checking a fifo count indicating the number of entries in the FIFO occupied by valid data; determining the next request type from the group consisting of word, sequential burst, fixed length burst and line transfer based on the transfer count and fifo count checks; and sending the transfer request. Alternatively, the method further includes the steps of: once the transfer request is sent, putting the next request on the bus of the PLB system; and based on a previous request type and the transfer count, determining a request type.
In accordance with a second aspect of the invention, there is provided an apparatus for optimising a bus in a Processor Local Bus (PLB) system. The apparatus includes:
a master engine for performing a transfer transaction of N bytes of data on the bus of the PLB system;
a device for determining a type of transfer to be performed by the master engine to optimize operation of the bus of the PLB system in response to a transfer request received asynchronously from a device coupled to the bus;
a FIFO coupled to the master engine for transferring data asynchronously between a device and the bus of the PLB system dependent upon the determined type of transfer.
In accordance with a third aspect of the invention, there is provided a computer program product having a computer readable medium having a computer program recorded therein for optimising a bus in a Processor Local Bus (PLB) system. The apparatus includes:
a computer program code module for providing a master engine for performing a transfer transaction of N bytes of data on the bus of the PLB system;
a computer program code module for determining a type of transfer to be performed by the master engine to optimize operation of the bus of the PLB system in response to a transfer request received asynchronously from a device coupled to the bus;
a computer program code module for transferring data asynchronously using a FIFO between the device and the bus of the PLB system dependent upon the determined type of transfer.